/* Port7
 #define SPI_EN_BIT                  BIT7
 #define SPI_EN_DDR                  DDRD
 #define SPI_EN_PORT                 PORTD
*/

//Port 8
#define SPI_EN_BIT                  BIT0
#define SPI_EN_DDR                  DDRB
#define SPI_EN_PORT                 PORTB

// PB4(MISO), PB3(MOSI), PB5(SCK), PB2(/SS)         // CS=1, waiting for SPI start // SPI mode 0, 4MHz
#define SPI0_Init()						DDRB  |= SPI0_SS_BIT|SPI0_SCLK_BIT|SPI0_MOSI_BIT;\
										PORTB |= SPI0_SS_BIT; PORTB &= ~(SPI0_SCLK_BIT|SPI0_MOSI_BIT);\
										SPCR  = 0x50; SPI_EN_DDR |= SPI_EN_BIT 
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//IInChip SPI HAL
#define IINCHIP_SpiInit					SPI0_Init
#define IINCHIP_SpiSendData				SPI0_SendByte	
#define IINCHIP_SpiRecvData				SPI0_RxData


#define IINCHIP_CS_BIT					BIT2
#define IINCHIP_CS_DDR					DDRB
#define IINCHIP_CS_PORT					PORTB

#define IINCHIP_CSInit()      (IINCHIP_CS_DDR |= IINCHIP_CS_BIT); (SPI_EN_DDR |= SPI_EN_BIT)
#define IINCHIP_CSon()        (IINCHIP_CS_PORT |= IINCHIP_CS_BIT); (SPI_EN_PORT &= ~SPI_EN_BIT)
#define IINCHIP_CSoff()	      (SPI_EN_PORT |= SPI_EN_BIT);(IINCHIP_CS_PORT &= ~IINCHIP_CS_BIT)